1. Field of the Invention
The present invention generally relates to cascode emitter coupled logic (ECL) circuits and, more particularly, to input voltage level conversion circuitry for three-level cascode logic circuits which make the three-level circuits compatible with a two-level circuit environment.
2. Description of the Prior Art
U.S. Pat. No. 4,760,289 to Eichelberger et al. discloses a two-level differential cascode current switch masterslice cell which is replicated in an array on a semiconductor chip. The masterslice cells are wireable to form any of a selected book set of basic logic circuits in a very large scale integrated (VLSI) circuit. The Eichelberger et al. circuit provides a twenty percent increased performance advantage over conventional emitter coupled logic (ECL) masterslice circuits running at the same power.
Three-level cascode circuits offer greater logic power for almost the same power dissipation when compared to two-level cascode circuits. In order for the three-level cascode circuit to work, however, three unique input levels are required. This generally requires higher supply voltage to avoid device saturation and excessive tolerance in the current source. Thus, the performance potential of three-level cascode masterslice circuits has not been realized because of the overhead associated with the supply voltage.